This test pattern generator improves detection of side-channel signatures caused by hardware Trojans to reveal potential attacks to System-on-Chip (SoC) devices. Detecting hardware Trojans is critical to ensuring the security and trustworthiness of SoC designs. Side-channel analysis is a common tool for detecting Trojans that analyzes various side-channel signatures such as power and current delay. Deviations in these signatures can identify malicious circuitry modifications. Generating the right circuitry test patterns that expose these modifications is a major challenge. For large SoC designs, test generation time grows exponentially with the design complexity, and Trojan-caused side-channel signatures are marginal compared to noise and process variations.
Researchers at the University of Florida have developed an efficient procedure to generate test patterns that maximize the sensitivity of side-channel analysis to Trojan signatures.
Reliable hardware Trojan detection using side-channel analysis to ensure secure SoCs
This test generation mechanism facilitates the exposure of malicious hardware and intellectual property (IP) modifications via side-channel analysis using dynamic current. The design formalizes test pattern generation as a searching problem and solves the optimization using a genetic algorithm. The process quickly finds the test patterns that best maximize switching in the suspicious circuitry regions while minimizing switching in the rest of the circuit. These tests dramatically improve the side-channel sensitivity during side-channel analysis, enabling it to identify Trojans in SoCs to avoid malicious IP attacks.
