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Supernet Overlay with High-Level Synthesis that Provides Software Developers FPGA Benefits

Compiles 10,000 Times Faster, Significantly Improving Productivity and Marketability of FPGAs

This supernet overlay integrated with high-level synthesis for field programmable gate arrays (FPGAs) offers quick compilation times that significantly improve productivity, broadening the market for FPGAs to benefit software designers. Forecasts suggest the market for FPGAs will be upwards of $7 billion dollars by 2022. FPGAs are integrated circuits designed to be configured by a customer or a designer in the field, thus the term “field programmable.” FPGA computing technologies offer advantages such as excellent performance and low power, but they lack in application-design productivity. Available high-level synthesis tools for FPGAs enable specialized programming languages but require hours or days to compile designs. Researchers at the University of Florida have created a supernet overlay, which is a virtual architecture integrated with high-level synthesis that makes compiling and reprogramming FPGAs 10,000 times faster. In addition, the fast compilation enables many runtime optimizations for hardware circuits, broadening use of FPGAs to designers currently using other technologies such as microprocessors or graphic processing units.



An overlay architecture for increased productivity in programming FPGAs



  • Compiles high-level code onto supernet overlays instead of directly onto an FPGA, resulting in a compilation speed that is 10,000 faster than existing tools
  • Improves productivity, reducing time-to-market of any product that uses FPGAs
  • Enables application portability across different FPGA devices and boards, broadening use for software developers


FPGAs are integrated circuits designed to be programmed by designers to meet their specific needs. In order to create a specific function, the FPGA uses logic elements and configurable interconnections between functional units to create a desired function. These supernet overlays use FPGA resources to define an application-specialized virtual architecture that hides the low-level details of the FPGA to simplify application design. Application developers then compile their applications onto the overlay instead of the FPGA. By integrating high-level synthesis with supernet overlays, this technology provides software developers with an FPGA tool flow that is similar to other technologies. Results have shown that this technology’s compiling and reprogramming speeds are 10,000 times faster than that of available tools, while also enabling portability across different FPGA devices and boards. Ultimately, this technology significantly increases FPGA productivity for software developers.

Patent Information:
App Type: Patent No.: Patent Status:
ORD/UTIL 10,516,396 Issued