Integrated Circuit Camouflaging to Protect Intellectual Property

Covert Gates Based on Doping and Dummy Contacts

This cell camouflaging design leverages doping and dummy contacts to create camouflaged cells indistinguishable from regular standard cells to provide greater protection of integrated circuits in cyber-attacks. Available methods of integrated circuit camouflaging based on standard cells assuming Boolean functions are vulnerable to invasive and non-invasive attacks. Although more secure than integrated circuits without camouflaging, these readily identifiable camouflaged gates are easy to hack. By quickly testing each cell, hackers figure out which cells yield erroneous netlists vs. which hold the valuable information. Foreign theft of American intellectual property costs hundreds of billions of dollars annually , suggesting the need for better cybersecurity methods.

Researchers at the University of Florida have created a camouflaging strategy that leverages the use of dummy contact cells to create a gate indistinguishable from regular logic gates in a design. These covert gates avoid giving erroneous information, preventing hackers from knowing which information is valuable when they attempt to reverse engineer the integrated circuit.

Application

Non-obvious camouflaging of integrated circuits by the use of modified logic gates, in order to protect semiconductor intellectual property

Advantages

• Requires only a minor change in integrated circuit fabrication, making the camouflaging strategy inexpensive
• Covert gates consume no more area than regular standard cells and do not hinder performance, incurring minimal overhead compared to available camouflaged gates
• Indistinguishable from standard cells under scanning electron microscope imaging, increasing complexity for would-be attackers
• Opportunity to choose nets in the design to connect to dummy inputs, increasing functional or logical difference between netlist recovered and original design

Technology

Integrated circuit camouflaging has emerged as promising solution for protecting semiconductor IP against reverse engineering. Using this covert-gate camouflaging strategy leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. In a comprehensive security analysis of covert gate, researchers have demonstrated these covert gates achieve high resiliency against SAT and test-based attacks at very low overheads.